Integrated circuits are manufactured by fabricating electrical devices on semiconductor substrates and interconnecting the various electrical devices. Shallow trench isolation (STI) is a technique used to electrically isolate transistors or electrical devices and is a facilitating technology for the fabrication of advanced microelectronic devices, for example, complementary metal-oxide-semiconductors (CMOS). STI has largely replaced localized oxidation of silicon (LOCOS) isolation methods in the fabrication of advanced microelectronic devices. STI involves creating oxide isolation trenches for electrical separation or segregation in integrated circuits in order to avoid electromechanical interference (EMI) and/or parasitic leakage paths between the various devices. The oxide trench is etched into the silicon substrate utilizing, for example, reactive ion etching (RIE), followed by employing a thermal oxidation process to line the trench walls with a thin layer of oxide, for example, SiO2. The trench is then filled with a gap-filling oxide isolation material. The structure is subsequently chemically mechanically polished (CMP) to create a planar STI structure such that electrical devices (inner active areas) can be formed within regions bounded by the STI, often referred to as moats.
The Wg (gate width) of small transistors, for example, static random access memory (SRAM) transistors is limited by the process constraints of the required “footprint” of the device. Given specific pitch and space limitations, the Wg of the SRAM is constrained within specific physical limits. A small gate width (Wg) can lead to small drive currents (ION) in minimum size transistors. An increase in drive current (ION) at no or a small increase in leakage current (IOFF), for a given “footprint”, would provide a significant benefit over the current available technology.
FinFET structures, currently being used in some of the smallest memory devices (e.g., SRAM), are not suitable for wide transistor type applications, for example, large switches. FinFET transistors generally have higher current densities than most CMOS devices; however, the fins of FinFETs are not as wide as the “fins” of wide transistors because most of the FinFET world is aimed at narrow transistors. FinFETs are typically less than 100 nm in width and therefore not suitable for wide transistor applications.
Thus, there exists a need for an improved system and method for creating wide transistors with increased drive current with little or no increase in leakage current. In other words, there exists a need for improving the drive current (ION) per unit width without a proportional increase in leakage current (IOFF).